Low-power frequency divider in 180 nm CMOS technology for 2.4 GHz phase locked loop applications

This paper presents the design and analysis of a low-power programmable frequency divider implemented in 180 nm CMOS technology, optimized for applications in the 2.4 GHz Bluetooth band. In the proposed architecture, a 32/33 dual-modulus prescaler, a main counter, and a swallow counter are integrated, utilizing true single-phase clock (TSPC) flip flops that enable high-speed operation with minimal power consumption. The design was simulated and evaluated using PSPICE software under a 2V supply voltage, demonstrating stable frequency division with low phase noise. Simulation results revealed a total power consumption of 0.58 mW, with efficient distribution across the prescaler and counter circuits. This work addresses key challenges in power efficiency, operational speed, and circuit area, making it a strong candidate for energy-constrained applications such as Bluetooth transceivers, wireless sensor networks, and IoT devices. With the proposed frequency divider, wireless communications systems can easily integrate PLL-based frequency synthesizers into their next-generation systems. This is a scalable, energy-efficient solution.